The present invention relates to a liquid crystal display device and, more particularly, to a liquid crystal display device which exhibits an improved production yield through elimination of disconnection in a wired laminated portion of an active matrix liquid crystal display device of the thin film transistor (TFT) type.
The liquid crystal display device has been widely utilized as a device for displaying a variety of images, including still images and moving images.
The liquid crystal display device is basically classified into two types, including the type (called the xe2x80x9csimple matrix typexe2x80x9d) wherein a liquid crystal layer is sandwiched between two substrates, at least one of which is made of transparent glass, and wherein a predetermined pixel is turned ON/OFF by applying a voltage selectively to various electrodes formed on the substrates for forming the pixels; and the type (called the xe2x80x9cactive matrix typexe2x80x9d in which thin film transistors (TFT) are used as the switching elements) wherein the various electrodes and pixel selecting switching elements are formed so that a predetermined pixel is turned ON/OFF by selecting the switching elements.
The active matrix type liquid crystal display device has grown to be the main type used for display devices because of its contrast performance and quick display performance.
In the active matrix type liquid crystal display device, the longitudinal field type is generally employed, in which an electric field for changing the orientation of a liquid crystal layer is applied between electrodes formed on one substrate and electrodes formed on the other substrate. In recent years, however, a transverse field type (In-Plane Switching Mode: IPS type) liquid crystal display device has been introduced, in which the direction of the electric field to be applied to the liquid crystal is generally in parallel with the substrate face.
FIG. 10 is an exploded perspective diagram for explaining the overall structure of the active matrix type liquid crystal display device using an orientation film according to the present invention.
FIG. 10 illustrates the specific structure of the liquid crystal display device (or the module having a liquid crystal display panel, a circuit substrate, a back light and other components integrated to form a module called a xe2x80x9cMDLxe2x80x9d) according to the invention.
Reference letters SHD designate a shield case (also called the xe2x80x9cmetal framexe2x80x9d) made of metal sheet; letters WD designate a display window; letters INS1 to INS3 designate insulating sheets; letters PCB1 to PCB3 designate circuit substrates (of which PCB1 is a drain side circuit substrate and a video signal line driving circuit substrate; PCB2 is a gate side circuit substrate; and PCB3 is an interface circuit substrate); letters JN1 to JN3 designate joiners for joining the circuit substrates PCB1 to PCB3 electrically; letters TCP1 and TCP2 designate tape carrier packages; letters PNL designate a liquid crystal display panel; letters GC designate a rubber cushion; letters ISL designate a shielding spacer; letters PRS designate a prism sheet; letters SPS designate a scattering sheet; letters GLB designate a light guide board; letters RFS designate a reflection sheet; letters MCA designate a lower case (or mold frame) formed by integral molding; letters MO designate an opening in the MCA; letters LP designate a fluorescent lamp; letters LPC designate a lamp cable; letters GB designate a rubber bushing for supporting the fluorescent lamp LP; letters BAT designate a pressure sensitive adhesive double coated tape; and letters BL designate a back light composed of the fluorescent lamp and the light guide board. The scattering sheet members are stacked in the illustrated arrangement to assemble the liquid crystal display module MDL.
The liquid crystal display module MDL includes two kinds of accommodating/holding members for the lower case MCA and the shield case SHD and is constructed by integrating the metallic shield case SHD accommodating and fixing the insulating sheets INS1 to INS3, the circuit substrates PCB1 to PCB3 and the liquid crystal display panel PNL, and the lower case MCA accommodating the back light BL composed of the fluorescent lamp LP, the light guide board GLB and the prism sheet PRS.
On the video signal line driving circuit substrate PCB1, there is mounted an integrated circuit chip for driving the individual pixels of the liquid crystal display panel PNL. On the interface circuit substrate PCB3, on the other hand, there are mounted an integrated circuit chip for receiving video signals from an external host and control signals, such as timing signals, and a timing converter TCON for generating clock signals by processing the timings.
The clock signals, as generated by the timing converter, are fed through a clock signal line CLL, which is laid on the interface circuit substrate PCB3 and the video signal line driving circuit substrate PCB1, to the integrated circuit chip which is mounted on the video signal line driving circuit substrate PCB1.
The interface circuit substrate PCB3 and the video signal line driving circuit substrate PCB 1 are multi-layered wiring substrates, and the clock signal line CLL is formed as an inner wiring line of the interface circuit substrate PCB3 and the video signal line driving circuit substrate PCB1.
Here, the liquid crystal display panel PNL is constructed by adhering two substrates, including the TFT substrate having TFTs and various wiring lines/electrodes, and the filter substrate having the color filter, and by sealing the liquid crystal in the clearance between the two substrates, such that the drain side circuit substrate PCB1 for driving the TFTs, the gate side circuit substrate PCB2 and the interface circuit substrate PCB3 are connected by the tape carrier packages TCP1 and TCP2, and such that the individual circuit substrates are connected by the joiners JN1, JN2 and JN3.
FIG. 11 is a schematic diagram for explaining the wired structure in the vicinity of one pixel of the TFT substrate forming the liquid crystal display device shown in FIG. 10. Reference numeral 1 designates a substrate; numeral 2 designates a scanning signal line (or gate line); numeral 2xe2x80x2 designates an adjacent scanning signal line (or adjoining gate line); numeral 3 designates a video signal line (or drain line); numeral 4 designates a source electrode; numeral 6 designates a pixel electrode; letters TFT designate a thin film transistor; and letters Cadd designate a capacity added element.
In FIG. 11, the central portion of the substrate 1, except for the periphery, provides a display region which is filled with a liquid crystal material in the clearance which is formed by joining the other substrate or the filter substrate to it.
In this display region, moreover, there are formed the scanning signal line 2 (or gate line), extending in an X-direction, and the video signal line 3 (or drain line), extending in a Y-direction. There is further formed a source electrode, which extends in the Y-direction while being insulated from the scanning signal line 2, which also extends in the X-direction.
Each region, as defined by the scanning signal line 2 and video signal line 3, forms one pixel.
In other words, the aforementioned display region is formed of a set of numerous pixel regions arranged in a matrix shape.
Each pixel region is composed of the thin film transistor TFT to be turned On when a scanning signal is fed from the scanning signal line 2 and the video signal line 3, so that the pixel electrode 5 is fed by the video signal from the video signal line 3 passing through the thin film transistor TFT, which is turned ON. In addition to the thin film transistor TFT and pixel electrode 5, the capacity added element Cadd is formed between the adjoining scanning signal line 2xe2x80x2, other than the scanning signal line 2 for driving the thin film transistor TFT, and the aforementioned pixel electrode 5.
This capacity added element Cadd is provided for storing the video signal for an extended time in the pixel electrode 5 even when the thin film transistor TFT is turned OFF.
In this kind of liquid crystal display device, the aforementioned wiring lines for selecting the pixels are formed over the substrate 1 by using various filming means and patterning means.
For the wiring lines of the active matrix liquid crystal display device of the thin film transistor type, there is employed a refractory metal which has few hillocks. This wiring material can be exemplified by chromium (Cr) or molybdenum (Mo) as a pure metal. An alloy material to be used is exemplified by an alloy of Cr and Mo or an alloy of Mo and tungsten (W).
Of the pure metals, Cr is excellent in its adhesion to the substrate and the resist and is featured by the fact that the etching end portion is formed at a right angle with respect to the substrate face when the wiring line is etched.
When the wiring lines (or lower layer wiring lines) are formed in the lowermost layer of the substrate by using a material having such characteristics, the so-called xe2x80x9cstep coveragexe2x80x9d at the vertical wall of the etching end is deteriorated by the insulating film or the like, as formed over the lower wiring lines. This causes problems, such as a deterioration in the breakdown voltage or disconnection of the portions where the lower wiring lines are crossed over by other wiring lines (or upper wiring lines) formed over the former.
FIG. 12 is a partial section for explaining the structure in the vicinity of a TFT, using as an example the construction of a conventional liquid crystal display device. As in FIG. 11, reference numeral 1 designates a TFT substrate; numeral 1xe2x80x2 designates a filter substrate; numeral 2 designates a scanning signal line (or gate electrode); numeral 3 designates a video signal line (or drain electrode 3); numeral 4 designates a source electrode; numeral 5 designates a pixel electrode; numeral 6 designates an insulating film; numeral 7 designates a semiconductor layer; numeral 7A designates a contact layer; numeral 8 designates a passivation film; numeral 8A designates a contact hole; numeral 9 designates a color filter; numeral 10 designates a black matrix; numeral 11 designates a smoothing layer; numeral 12 designates a common electrode; letters TFT designates a thin film transistor; letters Cadd designate a capacity added element; and letters LC designate a liquid crystal.
At the TFT portion over the TFT substrate 1 or one substrate, as shown in FIG. 12, the gate electrode 2, the insulating film 6, the semiconductor layer 7, the contact layer 7A, the drain electrode 3, the source electrode 4, the passivation film 8, the pixel electrode 5 and so on are stacked in a multilayered structure by filming them and by patterning with etching treatment. In the capacity added portion, on the other hand, the adjoining gate electrode 2xe2x80x2, the insulating film 6, the passivation film 8 and the pixel electrode 5 are likewise laminated.
As described hereinbefore, the gate electrode 2, as formed in the lowermost layer of the substrate 1, is made of either the pure Cr or a Crxe2x80x94Mo alloy and is worked at its end portion (or side end face) at a right angle with respect to the face of the substrate 1 by etching treatment. As a result, the insulating film 6, as formed thereover, is insufficiently covered at its edge portion, as shown, by the normal wall face.
Over the insulating film 6, there are formed the drain electrode 3 and the source electrode 4. At the portions where the drain electrode 3 and source electrode 4 ride over the gate electrode 2, the insulation gap or the film thickness becomes small, as shown, to cause problems, such as a drop in the breakdown voltage, short-circuiting or disconnection.
On the other hand, the wiring line made of pure Cr is troubled by the problem that its upper face is exposed to a dry etching atmosphere which tends to produce a fluoride, thereby to deteriorate the contact characteristics with the film formed thereover. When the wiring line is made of a Moxe2x80x94W alloy, the adhesion to the bed or substrate is weakened to raise a problem that the wiring line is easily separated by thermal hysteresis after being filmed.
A technique is disclosed in Unexamined Published Japanese Patent Application No. 7-301822 for solving the problem of the step coverage in the formation of a wiring line of this kind. In the technique disclosed, two alloy layers having different compositions of Cr and Mo are formed as the wiring line material by the sputtering method or the like so that the etched end portion may be right-tapered merely by making use of the difference in the etching rate between the lower layer and the upper layer.
In the publication described above, the adhesion to the substrate is similar to that which is obtained by using a Crxe2x80x94Mo alloy material. Although the problem of the step coverage has been solved, the problem of the separation of the wiring line from the substrate is still left unsolved so that a sufficient reliability cannot be achieved.
An object of the invention is to solve the aforementioned various problems inherent in prior devices and to provide a liquid crystal display device which is capable of providing improved reliability by improving the contact characteristics between the lower layer wiring line and the upper conductor film, by more sufficient step coverage of the upper film such as the insulating film, by improving the adhesion to the substrate and by preventing the cutting of the upper layer wiring line and the short-circuiting of the lower layer wiring line.
In order to achieve the above-specified object, the invention utilizes the difference in the corrosion rate due to the corrosion potential difference between different kinds of metals and is characterized by the following features (1) to (7):
(1) A liquid crystal display device is provided with a wiring line having a laminated structure over an insulating substrate, wherein said laminated structure includes a first layer made of a first metal layer and a second layer formed over said first layer and made of a second metal layer having the same principal component as that of said first metal layer, but a different added element and/or a different composition, and wherein said first layer has a side end face having a right-tapered shape, whereas said second layer has a side end face set at a right angle or is counter-tapered with respect to the substrate face.
(2) A liquid crystal display device is provided with one substrate having a plurality of wiring lines, including a scanning signal line, a video signal line and a pixel electrode, and an active element connected with said scanning signal line and said video signal line for controlling ON/OFF operation of the pixel; the other substrate including at least a color filter and which is adhered through a minute clearance to said one substrate; and a liquid crystal filled in the clearance between said one substrate and said other substrate,
wherein the wiring lines of at least said signal lines comprises a wiring line of a laminated structure formed on the side of said one substrate, wherein said laminated structure includes a first layer made of a first metal layer and a second layer formed over said first layer and made of a second metal layer having the same principal component as that of said first metal layer, but a different added element and/or a different composition, and wherein said first layer. has a side end face having a right-tapered shape, whereas said second layer has a side end face set at a right angle or is counter-tapered with respect to the substrate face.
(3) A liquid crystal display device according to feature (2), wherein said first layer is made of a pure chromium layer, whereas said second layer is made of an alloy layer containing chromium and molybdenum as its principal components.
(4) A liquid crystal display device is provided with one substrate having a plurality of wiring lines, including a scanning signal line, a video signal line and a pixel electrode, and an active element connected with said scanning signal line and said video signal line for controlling ON/OFF operation of the pixel; the other substrate including at least a color filter and adhered through a minute clearance to said one substrate; and a liquid crystal filled in the clearance between said one substrate and said other substrate,
wherein the wiring lines of at least said signal lines comprises a laminated structure formed on the side of said one substrate, wherein said laminated structure includes a first layer containing chromium and tungsten as its principal component and a second layer formed over said first layer and made of chromium and molybdenum as its principal components, and wherein said first layer has a side end face having a right-tapered shape, whereas said second layer has a side end face set at a right angle or is counter-tapered with respect to the substrate face.
(5) A liquid crystal display device is provided with one substrate having a plurality of wiring lines, including a scanning signal line, a video signal line and a pixel electrode, and an active element connected with said scanning signal line and said video signal line for controlling ON/OFF operation of the pixel; the other substrate including at least a color filter and which is adhered through a minute clearance to said one substrate; and a liquid crystal filled in the clearance between said one substrate and said other substrate,
wherein the wiring lines of at least said signal lines comprises a three-layered laminated structure formed on the side of said one substrate, wherein either the first layer or the third layer contains two kinds of metals having the same principal component, but a different added element and/or a difference composition, wherein said second layer is made of a metal having a principal component other than those of said first and third layers and which is capable of being selectively etched from said first and third layers, and wherein either of said first layer or said second layer is more etched back than the other.
(6) A liquid crystal display device according to feature (5), wherein said laminated structure has three layers of Cr, an Al alloy and a Crxe2x80x94Mo alloy.
(7) A liquid crystal display device according to features (1) to (6), wherein the uppermost layer and the underlying layer of said laminated structure have a film thickness ratio of 0.3 or less.
Here, the following features (8) to (13) can be further adopted as a process for making the above-specified wiring structures:
(8) Over the insulating substrate (will be simply called the xe2x80x9csubstratexe2x80x9d) of glass or the like, there is formed a wiring line having a two-layered laminated structure which includes a first layer at the substrate side and made of pure chromium (Cr) and a second layer overlying the first layer and made of a chromium and molybdenum (Crxe2x80x94Mo) alloy.
(9) Over the substrate or the underlying layer of SiO or the like formed on the surface of the substrate, there is formed through the pure chromium layer a wiring line which is made of the chromium-molybdenum alloy layer.
(10) There are arranged over the substrate a gate wiring line and a drain wiring line, the former of which is made of a laminated structure of the pure Cr layer and the Crxe2x80x94Mo alloy layer and the latter of which is made of a single-layered structure composed of a laminated wiring line similar to that of the gate wiring line or the Crxe2x80x94Mo alloy layer.
(11) The gate wiring line is made of a laminated structure composed of a pure Cr layer and a Crxe2x80x94Mo alloy layer, whereas a pixel electrode is made of an indium/zinc oxide (ITO) so that an added capacity is formed by sandwiching an insulating layer in between.
(12) A wiring line of the aforementioned two-layered laminated structure is formed over the substrate, and its lower layer has a side end face right-tapered, whereas its upper layer has a side end face set at a right angle or is counter-tapered with respect to the substrate face.
(13) A laminated structure film having two kinds of wiring materials of different compositions is dipped in an etching liquid (etchant) so that the wiring line is right-tapered at its side end face by setting the corrosion potential of the second layer (or upper layer) of the laminated structure lower in the liquid than that of the first layer (or lower layer) thereby to set the etching rate of the first and second layer interface different than that of the first layer by the electrochemical reaction.
In the wiring line having the aforementioned two-layered laminated structure, the lower pure Cr layer is featured to have an excellent adhesion to the substrate or the bed layer. On the other hand, the upper layer of the Crxe2x80x94Mo alloy is enabled to have a lower specific resistance of the materials and a lower contact resistance to the upper layer than those of the pure Cr layer by introducing Mo and Cr having low specific resistance into the alloy.
Another advantage is that the film stress can be drastically lowered, as compared with a pure Cr layer, by making the alloy of Mo and by optimizing the sputtering condition.
By establishing a difference in the corrosion potential between the upper layer and the lower layer, moreover, the interface between the upper layer and the lower layer is etched earlier than the lower layer due to the corrosion potential difference, i.e., by the electrochemical reaction inbetween when the two layers are dipped in the common etchant. The side etching proceeds fastest at the interface between the upper and the lower layer. As a result, the side etching proceeds in the upper layer but proceeds earlier at the upper portion than at the lower portion in the lower layer.
FIG. 5 is a schematic diagram for explaining a state in which the etching proceeds by electrochemical reaction with a difference in the corrosion potential between the upper layer and the lower layer.
A wiring layer having a two-layered laminated structure is formed over the substrate 1 and is composed of a first layer 2A and a second layer 2B. And, the first layer or the lower layer is made of pure chromium (Cr), whereas the second layer or the upper layer is made of a chromium-molybdenum (Crxe2x80x94Mo) alloy. Then, by setting the corrosion potential of the first layer 2A in the etchant high (H) and the corrosion potential of the second layer 2B low (L), an electrochemical reaction is caused between these two layers when they are dipped in the etchant. By this electrochemical reaction, the etching proceeds, as indicated by arrow E. Furthermore, by setting the corrosion potential of the first layer low and the corrosion potential of the second layer high, similar etching proceeds.
Under the influence of the electrochemical reaction, the etching rate takes its maximum at the interface between the upper and lower layers so that the lower layer 2A is worked at its whole side end face into a right-tapered shape, i.e., a taper which extends in a direction away from the face of the substrate; whereas the upper layer 2B is worked at its side end face into either a shape normal to the face of the substrate 1 or a slightly counter-tapered shape which is a direction opposite to the taper of the lower layer.
When the etching rate of the upper layer is thus relatively accelerated by the electrochemical reaction between the upper and lower layers of two kinds of different compositions, the side-etching of the upper layer has to proceed even while the lower layer is being etched. This makes it necessary to make the upper and lower layers of either from an identical alloy group or such a material as can be etched with an identical etchant even if made of different metals, so that the etching of the two layers may proceed with the same etchant.
If the corrosion potential difference of the two layers is excessively large, moreover, the upper layer is exclusively etched abruptly, but the etching of the lower layer does not proceed or takes a small taper angle if etched. It has been experimentally found that the desirable corrosion potential difference between the upper and lower layers is set at 3 mV to 300 mV.
The desired taper angle has been achieved within that range, especially from 5 mV to 200 mV.
If this condition is satisfied, a wiring line having the desired taper shape can be formed by making the upper layer and the lower layer into a laminated structure even if the etching rate of the composition of the lower layer is higher than that of the upper layer. The combination of the first and second layers may be other than that of pure Cr and a Crxe2x80x94Mo alloy. Similar effects can also be obtained from a laminated structure which is made of a Crxe2x80x94W alloy and pure Cr by adding W in place of Mo. Moreover, the corrosion potential difference of the two layers may be controlled by adding different second elements to the two layers. When the first layer is made of a Crxe2x80x94W alloy, whereas the second layer is made of the Crxe2x80x94Mo alloy, for example, a corrosion potential difference can be established between the layers of the laminated structure to give the individual layers functions other than the corrosion potential. In the case of this combination, for example, the film stress can be lowered in the first layer, and the contact resistance to the overlying layer can be reduced in the second layer.
By thus tapering the side end faces of the wiring line to be formed over the substrate, it is possible to improve the step coverage of the insulating film to be formed thereover. It is further possible to solve the problems, such as the deterioration in the insulating breakdown voltage, the cracks which might otherwise be caused in the thin film (or CVD film) such as the CVD insulating film at the portions where the lower layer wiring line is ridden over by another wiring line (or upper wiring line) formed at the upper portion, or the disconnection of the drain wiring line or the source wiring line to be formed thereover.
Here, with an etching treatment which makes use of the aforementioned electrochemical reaction, and with the small thickness of the upper layer, the defects in the step coverage of the film to be formed over the upper layer can be avoided even if the upper layer has a side end face set at a right angle or is counter-tapered with respect to the substrate face.
FIG. 6 is an explanatory diagram of a change in the length of cracks to extend in the CVD film formed in the gate wiring portion when the film ratio between the upper layer and the lower layer is changed. The abscissa indicates the ratio a/b between the film thickness a of the lower layer and the film thickness b of the upper layer, and the ordinate indicates the crack length (nm). Here in the section of the film, CL designates cracks.
Here, the thickness of the film to be formed as the insulating film 6 by the CVD method is usually 300 to 400 nm.
When the thickness a of the upper layer is larger the thickness that b of the lower layer, that is, when the ratio a/b is no less than 1, the coverage of the gate electrode 2 with the insulating film 6 is so poor as to cause long racks.
As the ratio a/b decreases, on the contrary, the cracks become harder to cause so that the breakdown voltage between the gate/drain is improved.
It is clear from FIG. 6 that the crack length exceeds 300 nm for an a/b no less than 0.1, but exceeds 400 nm for an a/b no more than 1.0.
By making the film of the upper layer 2B thin to provide an a/b ratio of no more than 0.3, moreover, the cracks can be completely eliminated or reduced to a state of no practical problem. When the film thickness of the lower layer 2A is set to 200 nm, for example, an excellent coverage having no substantial crack can be realized for a film thickness of the upper layer 2B of no more than 60 nm.
For a smaller film thickness of the upper layer 2B, it is possible to further reduce the influence of cracks in the insulating film to be formed over the upper layer 2B. Since the film thickness indispensable for forming the thin film all over the substrate is 10 nm or more, however, it is desired to set the film thickness of the upper layer 2B at a value from 10 nm to 60 nm. When the film thickness of the upper layer must be thickner than 60 nm, the combination of taper-etching, which utilizes electrochemical reaction, and another taper-etching method, which utilizes penetration of etchant at the interface between photo-resist and the upper layer is available.
FIG. 7 is an explanatory diagram of the result of a change, as measured by changing the Mo concentration, in the corrosion potentials of pure Cr and a Crxe2x80x94Mo alloy in an aqueous solution of ceric nitrate.
The corrosion potential is at 1,150 mV for pure Cr, that is, when the Mo concentration is 0, and at 1,100 mV for the alloy containing Cr-50 Wt. % of Mo. By making use of the potential difference between the two, it is possible to effect the taperetching shown in FIG. 6. Here, the corrosion potential of the pure Mo is as low as 360 mV so that the corrosion potential of the Crxe2x80x94Mo alloy becomes lower for a higher Mo concentration.
FIG. 8 is an explanatory diagram of a change in the taper angle when the composition of the Crxe2x80x94Mo alloy to be combined with the pure Cr is changed.
When the Mo concentration is low, as shown, that is, in the case of the pure Cr, the wiring line is exclusively made of Cr so that the taper angle takes a value of 90 degrees (or normal to the substrate face). When the laminated layer of Crxe2x80x94Mo is made by adding Mo, the taper angle is lowered so that a taper angle of 40 to 60 degrees is obtained by adding 10 to 65% of Mo. For the composition of Cr-50 Wt. % of Mo, the taper angle is 55 degrees. As the Mo concentration of the upper layer rises to increase the corrosion potential difference between the two layers, the taper angle of the lower layer is hardly changed, but the upper layer tends to be counter-tapered, so that the overall shape is poor. It is therefore recommended that the Mo concentration is selected within a range of 10 Wt. % to 60 Wt. %.
According to the invention based on the technical items thus far described, it is possible to improve the taper angle distribution drastically in the substrate face.
In the tapering case making use of impregnation of the etchant into the clearance between the photoresist and the metallic thin film, on the other hand, the taper angle may be dispersed so largely reflecting the interface dispersion of the adhesion between the photoresist and the metallic thin film as to be doubled between the central portion and the peripheral portion. In the case of the embodiment, on the contrary, the aforementioned corrosion potential difference is determined by the material employed. According to the invention, by making use of the potential difference between the upper layer film and the lower layer film, therefore, the in-face dispersion of the taper angle of the etching treatment can be limited within xc2x19%.
When the invention is applied to the formation of a gate wiring line in an inverted stagger type TFT, the step coverage of an insulating film (or gate insulating film), an a-Si semiconductor film or a drain wiring line of SiN to be formed over the gate wiring line is improved to raise the breakdown voltage and to reduce the percent of defects, such as the disconnection of the drain wiring line.
Moreover, the upper layer containing the added Mo is hard to remain a fluoride and to oxidize in the oxidizing atmosphere, even dry-etched with a fluorine containing gas, so that its contact with another over electrode can be kept satisfactory.
The two layers for establishing the corrosion potential difference between the laminated films need not directly contact each other at all times, but similar effects can be achieved if the two layers are in contact through a conductive layer. It is therefore possible to make a three-layered structure in which a conductor layer of Al to be selectively etched with Cr is sandwiched between the Cr layer and the Crxe2x80x94Mo layer. At this time, when the uppermost Cr layer is etched at the time of etching the lowermost Cr layer or Crxe2x80x94Mo layer, an electrochemical reaction can be effected inbetween to etch one of them backward in a preferential manner. The shape to be obtained becomes different depending upon which of Cr and Crxe2x80x94Mo is employed as the uppermost layer, as shown in FIGS. 9A to 9C.
FIGS. 9A to 9C are explanatory diagrams of etched shapes of the two- or three-layered structure. When a film having a low corrosion potential is employed as the uppermost layer, as shown in FIG. 9A, the uppermost layer retracts from the Al, but this retraction can be suppressed. As a result, the overhang of the Al from the lower layer of Cr can be reduced to smooth the entire wiring line as a whole.
When a film having a low corrosion potential is employed as the lowermost layer, on the other hand, the retraction of the lowermost layer is promoted whereas the retraction of the uppermost layer is suppressed, as shown in FIG. 9B. As a result, the Al surface other than the end portion can be covered with the Cr to suppress the growth of a hillock of the Al from the end portion.
When the entire wiring line has a smooth sectional shape, the film construction may be made, as shown in FIG. 9A. When the hillock from the Al film is to be prevented, on the other hand, the film construction may be made as shown in FIG. 9B. Here, FIG. 9C shows an example of the prior art, in which only the Al layer protrudes to raise the problems in the overall shape and the anti-hillock requirement.